The invention relates generally to MOS (metal oxide semiconductor) memories, and is particularly directed to an improved, high speed, low power static MOS RAM (random access memory).
MOS memories generally include an orthogonal array of memory cells for storing data in the form of binary ones and zeros. Data can be written into or read from each memory cell by accessing a particular cell via row and column addresses applied to the memory.
Typically, a particular memory cell is accessed by means of a pair of bit lines and a word line which are selected by a column address and a row address, respectively. A memory cell which is located at the intersection of the selected bit lines and word line is thus accessed, and the binary data stored in the memory cell may be read out via the bit lines. Data is written into a memory cell in the same general manner.
The speed with which data can be written into or read from a memory cell depends in part on how rapidly the logic levels on the bit lines can change. For example, if a bit line has a low logic level after reading the data in a first memory cell, the bit line may have to change to a high logic level on reading the data from a next memory cell. A significant time is required for the bit line to accommodate such a change in logic levels, thereby limiting the RAM's operating speed.
Another problem associated with conventional static RAMS is the undesirably large amount of power used in constantly "pre-charging" their bit lines. Typically, the bit lines in both static and dynamic RAMS are pre-charged by coupling them to a source of potential equivalent to a high logic level. Such pre-charging is necessary because, if the bit lines have logic levels which are opposite to the logic levels of the next memory cell to be accessed, coupling the bit lines to that memory cell may flip the state of the cell. Pre-charging both bit lines high before row selection prevents a high logic output of a cell from being forced low by the potential on a bit line and prevents a cell's low logic output from being flipped high.
In dynamic RAMS, such pre-charging is a function necessary for the operation of the device and is accomplished synchronously for a short interval prior to row selection. However, because static RAMS operate asynchronously, they cannot be pre-charged at a periodic rate. For this reason, the bit lines of static RAMS are usually maintained in a state of constant pre-charge, except perhaps for a brief interval during read or write operations. Consequently, conventional static RAMS have dissipated much more power in their precharging operation than is desirable.